Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
The formation of stacked nanowires is an important step for decreasing the feature sizes of semiconductor devices.
One important issue is to reduce the parasitic capacitance due to overlap between the gate and source-drain region of a transistor.
In order to minimize this parasitic capacitance, the formation of an internal spacer has to be an integral part of the nanowire integration scheme.
Forming the internal spacer, however, may be process and/or material intensive. There is therefore room for improvement in the methods for forming the internal spacers.